This invention relates in general to analysis of digital circuit designs and more specifically to a system for modeling clocks during digital circuit design verification.
Today's approaches to simulation, testing and verification of digital circuit designs typically use a hardware design language (HDL) description of a circuit, gate array or other electronic devices or components. Examples of HDLs include, e.g., Verilog, AHDL, VHDL, etc. Once an HDL description of the circuit exists the description can be used in test bench simulations and verification to determine whether the circuit design performs correctly.
Simulations allow a circuit description to be modeled at a very detailed level. Digital logic errors, or “exceptions,” can be determined. Complex simulation and modeling also takes into account electrical, electromagnetic and other types of physical effects that could cause problems with the physical circuit once the circuit description is constructed. Due to the extremely large size of many of today's circuits (e.g., millions of transistors) and the enormously complex behavior of physical systems modeling, the sole use of highly detailed simulation and modeling can not be used to investigate all possible errors at all times for all states of a circuit.
One technique to make testing of hardware descriptions of large circuits feasible is called “verification.” Verification can be achieved by formal verification methods which include exhaustive mathematical and analytical techniques. This allows logic errors to be detected without complex simulation and modeling. For example, if it is known that certain logic states should not occur in the design then the detection of such states during verification can be the basis for investigation as to how or why an exception state occurred.
Another use for verification is to determine states from which to perform additional analysis. For example, if an error condition occurs a short while after starting simulation from a specific initial state then it is useful to begin analysis at the specific state. Information about the error condition can be obtained more quickly, especially with complex modeling and simulation, by starting from the specific initial state rather than starting from an arbitrary state. However, determining, identifying, managing and searching states during verification is, itself, a huge and complex task.
One problem with accurately obtaining state information for formal verification is trying to model the clock specification of a circuit description. The clock specification describes all of the clocks in a system or device under test. It is critical to obtain correct initial state and then maintain proper clock timing to derive subsequent states.